Arkprocessor learning labOpen simulator
About Ark

Computer architecture becomes learnable when state stops being invisible.

Ark is an educational processor lab. It connects code, execution, machine state, guided practice, and verified AI help without hiding the architecture behind an abstraction.

Explore the simulator
Why we built it

From reading diagrams to running ideas.

Architecture courses ask students to connect source code, encodings, datapaths, memory, and control flow. Those connections are difficult to form when every piece lives in a different tool—or when the machine only appears after an error.

Ark keeps those layers in one place. A student can step a single instruction, watch its effects, test a hypothesis, and ask for an explanation grounded in the processor that is actually open.

How Ark-U is built

A browser-native continuation, not a disconnected rewrite.

The web product is guided by the project’s own original instruction documentation.

VESP family

Nine defined stages—from the 1.0 foundation through 3.1RR—form one progressive learning path.

A custom scalar core

The project’s own instruction architecture supplies the scalar, stack, control, and graphics semantics.

Ark-U

The browser profile turns that architecture into an inspectable lab with source, state, display, lessons, and AI verification.

Product principles

What Ark promises students and instructors.

The processor is explicit

No silent fallback changes a student’s target. Saved files, AI runs, lessons, and history retain their processor identity.

Feedback comes from execution

Lesson outcomes and code-changing AI answers are grounded in bounded processor runs, not textual confidence.

The first experiment is open

Guests can use the complete simulator and practice lab. An account is needed only for AI and account-synced projects.

Boundaries stay visible

Unsupported instruction families and deployment-dependent features are named honestly instead of simulated by implication.

Current processor lab

Four paths, one architecture-neutral workspace.

PathSource formLearning focus
MIPS32AssemblyClassic RISC, syscalls, memory, control flow
RV32IMAssemblyOpen ISA, ABI calls, integer multiply/divide
VESP 1.0–3.1RR16-bit wordsFetch/decode/execute progression across nine stages
Ark-UArk-U syntaxCustom ISA, operand stack, control, and layered graphics
Ready to explore?

Open a processor and make one instruction matter.

Open Ark